Waymo's 1,000-TOPS ASICs Are Impressive—and Not a Benchmark

Waymo has disclosed that its purpose-built 5-nanometer ASICs deliver more than 1,000 TOPS—trillion operations per second—for sensor front-end processing and machine-learning models. The number sounds like a benchmark result. It is not one.

The disclosure does not identify the numerical precision behind the count, any sparsity assumption, memory bandwidth, sustained power, utilization, cost, or independently reproduced latency. Waymo itself points readers toward the more useful question: how much performance the complete system achieves in low-batch operation, from the first sensor input to an action.

Peak TOPS is one capacity input, not a system result. Without end-to-end latency, batch behavior, data movement, energy and thermals, resilience, and quality at achieved performance, two accelerators with the same headline can be unsuitable for each other’s workloads—or impossible to compare at all.

What Waymo disclosed, and what remains unknown

In its August 20 engineering post, Waymo says its onboard computer processes raw lidar, radar, and camera streams, pairs custom ML hardware with CPUs, GPUs, and other accelerators, and handles 13 high-resolution cameras simultaneously. It describes a liquid-cooled system with two independent compute engines that normally run parallel workloads and can take over after a fault.

The custom ASICs sit near the front of that pipeline. Waymo says they process and fuse raw sensor data, perform work including temporal denoising for low-light perception, and feed a purpose-built inference engine running sensor-fusion models. The wording matters: the company says these ASICs, plural, deliver more than 1,000 TOPS. It does not state how many chips contribute to the number or give a per-chip figure.

Reuters independently reported that the custom silicon is in production in Waymo’s latest robotaxi generation and that TSMC manufactures it on a 5 nm process. Reuters repeated a comparison with Nvidia’s current autonomous-driving systems, but the public evidence does not provide matched precision, workload, power, or latency conditions for that comparison.

Known and undisclosed details in Waymo’s custom edge AI compute announcement

Publicly disclosed	Still undisclosed	Why the gap changes a decision
More than 1,000 aggregate TOPS from custom ASICs	Precision, sparsity, operation-counting rules, chip count, and utilization	The peak figure cannot be normalized or converted into achieved model speed.
5 nm process and sensor front-end role	Die size, memory capacity and bandwidth, interfaces, yield, and cost	Node size alone does not reveal data-movement limits or system economics.
Low-batch emphasis and lower pixels-to-actuation latency	Workload, test procedure, latency values, distributions, and independent reproduction	A latency claim cannot be compared without the same input, quality target, and percentile.
Liquid cooling and redundant compute engines	Sustained watts, thermal limits, failover time, degraded capacity, and recovery tests	Peak operation and fault-tolerant operation may have different performance envelopes.

The Next Web’s independent review reaches a useful boundary: Waymo still names Nvidia and AMD among its suppliers and calls the complete computer a heterogeneous system. The custom silicon adds a specialized front end; the disclosure does not support the simpler claim that one new chip replaces the rest of the onboard computer.

1. 1

   Peak claim

   Operations per second under undisclosed conditions

2. 2

   Achieved accelerator work

   Useful model work after precision, sparsity, and utilization

3. 3

   System outcome

   Correct decisions delivered inside the real latency and power envelope

• LatencyEnd to end, including tail percentiles
• BatchConcurrency and arrival pattern
• DataSensor input and memory movement
• EnergySustained power and thermal limits
• ResilienceDegraded mode and recovery
• QualityAccuracy at achieved performance

TOPS counts arithmetic, not a deadline

One TOPS means a trillion counted operations per second. That is a property of an accelerator under specified conditions, not the time an application takes to produce a correct result.

Even a rough conversion needs more information. If a model path requires N counted operations and the accelerator has peak rate P, its idealized compute floor is N / P. A real path is closer to:

end-to-end time = input + preprocessing + model compute + data movement
                + postprocessing + scheduling + action

model compute ≈ counted operations / (peak rate × achieved utilization)

Neither line is a prediction for Waymo. They expose what a TOPS headline omits. Numerical precision changes how much arithmetic a chip can issue. Structured sparsity may let hardware skip selected zero-valued work. Utilization falls when a model cannot keep all units busy. Memory transfers, sensor ingestion, orchestration, and postprocessing may dominate even when the accelerator is fast.

Batch size changes the answer again. A data-center service can group requests to raise throughput, accepting some queueing and per-request delay. A vehicle processing a new sensor frame cannot wait indefinitely for a profitable batch. The JAX Scaling Book’s inference chapter makes the same general distinction for transformer serving: latency becomes a first-class objective during inference, while batching and parallelism reshape throughput.

This is why the 1,000-TOPS number is interesting but incomplete. It says Waymo has designed substantial specialized arithmetic capacity. It does not say how rapidly or efficiently the vehicle turns one set of sensor inputs into one acceptable action.

Comparable TOPS requires comparable conditions

A defensible comparison needs the same workload and quality threshold, numerical precision and sparsity rules, batch and concurrency pattern, latency boundary, power and cooling conditions, operating mode, and software stack. If those conditions do not align, the numbers describe separate system profiles rather than a winner and loser.

Waymo has said it will discuss its compute work at Hot Chips. As of the evidence check for this article on August 24 at 08:10 Asia/Jakarta, the public engineering post still leaves the comparison-critical specifications above unresolved. Future material could fill some rows: precision mix, memory bandwidth, sustained power, achieved latency distributions, model-quality gates, or degraded-mode results.

Until then, the omission is itself the conclusion. Waymo has disclosed a serious custom-silicon program and a system architecture shaped by latency, cooling, and redundancy. It has not published a reproducible benchmark. Another product with a 1,000-TOPS label would not complete the comparison; the measured system outcome behind either number remains unknown.

Sources

1. Waymo: A look under our trunk—what’s in our compute
2. Reuters: Waymo builds custom chip for robotaxis
3. The Next Web: Waymo built its own robotaxi chip and published its supplier list
4. MLCommons: A new automotive benchmark for MLPerf Inference v5.0
5. MLCommons: MLPerf Inference Edge benchmark
6. JAX Scaling Book: All About Transformer Inference